Power conservation is a well-known objective in many computer system designs. One conventional solution is to use monitor functions to enable a central processing unit (CPU) core to enter a low-power mode in certain circumstances. For example, in multiprocessor systems where multiple CPU cores access interdependent data in a table, only one CPU core is allowed to access and modify the data at a given time. This ensures consistency in the data. Accordingly, while one CPU core accesses the data, the other CPU cores must wait until the CPU core has completed any write operations to the data. After requesting access to the data, a given CPU core enters a low-power mode as an alternative to the CPU core being busy waiting for the data to become available. The CPU core then exits the low-power mode when the data becomes available.
While the CPU core is in a low-power mode, the CPU core must be able to monitor when the data becomes available. Some Intel x86 processors support monitor functions through so-called MONITOR/MWAIT instructions. These instructions provide an address range that can be monitored for each CPU core, and these instructions prompt a given CPU core to exit a low-power mode upon any coherent write to an address within the address range. The CPU cores include monitor logic that utilizes these instructions to monitor their bus interfaces to detect access to the monitored address range. A limitation with conventional solutions is that in the low-power mode, the monitor logic and bus interfaces of a given CPU core both need to remain active in order to continue monitoring. The other portions of the CPU core can enter a low-power mode while waiting for a requested resource in order to conserve power.
Accordingly, what is needed is an improved system and method for conserving power. The present invention addresses such a need.